Descripción del empleo

* Hi-Tech Start-up company|Senior role


We are a start-up company that is working on one of the most exciting and technically challenging projects in Europe right now… designing the microprocessors to power supercomputers.

We are a young and rapidly growing company, we welcome people who have a team-building mindset and who are eager to build the identity of the structure across multiple sites!

As a Senior Design Verification engineer you will report to the verification manager and will have the opportunity to be a driving force of the verification effort. Your day-to-day work will entail the following:

* Reading and analysing the system requirements and architecture requirement documents
* Plan for functional verification activities for a given subsystem/functionality
* Verification environment development and maintenance in SystemVerilog/UVM/SystemC/C++
* Tests writing in embedded C and debug
* Participation to verification methodology improvements
* Project milestones and deliverables planning with respect to functional verification within the company and with external partners
* Organize work and deliverables between skills, internal and external teams
* Opportunities for mentoring and training the next generation of verification engineers
* Opportunities to manage teams from external partners


Oportunidades de carrera y desarrollo profesional.#LI-DNP
Requisitos mínimos

We are particularly looking for engineers with at least 4 years of experience in:

* Verification of complex SoC or IP
* Experienced in:
* SystemVerilog/UVM/VHDL
SystemC/C++
* Some previous experience in Firmware based verification is a good to have
* Some knowledge of scripting languages like Bash/Perl/Python
* Use of verification management tools


Experience in the following are a plus:

* Experience in Firmware-based verification
* Knowledge in metrics-driven verification
* Use Git/Gitlab
* Insights of AMBA and other ARM Ips or standard peripherals like PCIe, DDR, HBM …


All applications from individuals with some experience in FPGA/ASIC development flows will be considered.Fluent English written & spoken is a must.